Junior Digital IC Layout & PnR Engineer (Leuven)

ICsense NV; Town of Belgium (WI); Vor Ort; USD 47.868 - 63.824; Vollzeit

Benefits dieser Stelle

Attractive salary package with extra福利

Team activities

Growth opportunities

Zusammenfassung

ICsense NV in Leuven seeks a Junior Digital Physical Design / PnR Engineer to perform and organize the digital physical design of ASICs, collaborating with analog layouters and project leaders to ensure high-quality layouts.

You will set up and maintain the tool flow for place & route and physical synthesis, assist with floor planning, and grow in areas like SSTA, DFT, and verification. A master’s in EE and fluency in English are required.

Qualifikationen

• Master's degree in electrical engineering (preferably chip design).
• Dynamic and highly motivated engineer.
• Willingness to learn digital physical design, floor planning and P&R for multiple power/domains (UPF) and multiple clock-domains.
• Interest to learn digital synthesis, STA, and physical verification.
• Strong communication and reporting skills in English.
• Experience with front-end RTL design in VHDL/Verilog/SystemVerilog (plus).
• Experience with scripting languages such as Python and TCL; C (plus).

Aufgaben

• Physical design of digital ASICs (place & route) following design rules.
• Collaborate with analog layouters, digital designers and project leaders.
• Organize deliverables and timings for digital/mixed-signal layouts to ensure high quality.
• Top-level assembly of ASICs with digital and analog parts, considering DFT.
• Set up and maintain tool flow for place & route and physical synthesis.

Kenntnisse

Strong communication and reporting

Willingness to learn digital physical

Python scripting

TCL scripting

English proficiency

RTL design experience (VHDL/Verilog)

C language familiarity

Ausbildung

Master’s degree in electrical engineering

Tools

Python

TCL

C

Jobbeschreibung

ICsense NV in Leuven seeks a Junior Digital Physical Design / PnR Engineer to perform and organize the digital physical design of ASICs, collaborating with analog layouters and project leaders to ensure high-quality layouts.

You will set up and maintain the tool flow for place & route and physical synthesis, assist with floor planning, and grow in areas like SSTA, DFT, and verification. A master’s in EE and fluency in English are required.