Physical ASIC Design Implementation Engineer

VeroTech; Vlaams-Brabant; Hybride; EUR 70 000 - 110 000; Plein temps

Avantages offerts par ce poste

Meal vouchers

Insurance

Company car

Remote work options

Résumé du poste

VeroTech is seeking a Physical ASIC Design Implementation Engineer to work on projects spanning from 2N to 180nm. You will own the backend flow from netlist to GDSII-out using Cadence Innovus Place & Route.

You will partition top-level data into sub-block constraints, drive timing closure, and coordinate with clients through the design cycle. The role offers remote work options, meal vouchers, insurance, and a company car. This is an engaging team environment with opportunities for growth.

Qualifications

• Strong background in physical ASIC design implementation.
• Experience with Cadence Innovus Place&Route flow and full backend: netlist to GDSII.
• Experience with low power design and SDC/debugging.
• Familiarity with sign-off processes and timing/power analysis.

Responsabilités

• Liaise with customers for project specifications and execution.
• Lead top-level and block-level design tasks, sign-off, and flow setup.
• Partition and constrain top-level data into sub-block timing constraints.
• Coordinate with Physical Design team for signoff and flow setup.
• Perform placement, CTS, routing, and fix setup/hold violations.
• Execute sign-off extraction, timing and power analysis.

Connaissances

Netlist to GDSII-out understanding

Low power design (UPF)

Top-level/block-level design

Sign-off processes

Partitioning sub-block data

Client communication

Outils

Cadence Innovus Place&Route

Description du poste

Join our innovative team as a Physical ASIC Design Implementation Engineer, where you'll work on cutting-edge projects spanning a range of technologies from N2 to 180nm. Leverage your expertise in the full backend process, from netlist to GDSII-out, and become an integral part of advancing our client’s technological capabilities.

About The Role

As a Physical ASIC Design Implementation Engineer, you will be involved in a dynamic environment working on top-level chips and block-level designs. You will be responsible for managing direct communication with clients, tailoring solutions to their specifications, and ensuring seamless execution throughout the design cycle with full Cadence Innovus Place&Route flow understanding. Your role will involve partitioning tasks, driving signoff closure, and leading technical discussions.

Key responsibilities

• Liaise with customers for future project specifications and execution
• Demonstrate full proficiency in Cadence Innovus Place&Route flow
• Lead partitioning and division of the top-level SDC file into timing constraints for sub-blocks
• Collaborate with the Physical Design implementation team for signoff closure.
• Manage technical communication with customers regarding their specifications
• Set up flows for specific library sets and foundry nodes
• Develop low power designs (UPF) and debug SDC files
• Expertise in Floorplanning & power grid
• design for top-level and block-level tasks
• Conduct Placement, CTS & Routing, and solve setup & hold violations
• Execute sign-off extraction, timing, and power analysis
• Perform physical verification, equivalence checks, and more

What we're looking for

• We seek a skilled professional with a strong background in physical ASIC design implementation and experience in Cadence Innovus Place&Route flow
• Excellent understanding of chip design from netlist to GDSII-out
• Proven ability in partitioning and dividing top-level data into sub-block constraints
• Experience with low power design and SDC file debugging
• Familiarity with various verification methods and sign-off processes

At VeroTech, we empower engineers to grow, innovate, and lead. Join a dynamic community where you’ll work on cutting-edge R&D projects, receive personalized career development, and thrive in a supportive, inclusive culture. Enjoy flexibility with remote work options, a competitive salary package, and additional benefits like meal vouchers, insurance, and a company car. Be part of impactful projects that shape the future of technology while maintaining a healthy work-life balance.

Benefits

• flexibility with remote work options
• competitive salary package
• meal vouchers
• insurance
• company car

Ready to inspire?