Staff Engineer - Digital Design

Cyient; Vlaams-Brabant; On-site; EUR 60,000 - 90,000; Full time

Job summary

Cyient in Belgium seeks an experienced RTL Design Engineer to create advanced digital building blocks for power management and low-voltage applications.

You will contribute to micro-architecture, RTL development using VHDL/Verilog/SystemVerilog, and collaborate with analog, verification, and physical design teams to ensure timing and power goals are achieved.

Qualifications

• 4 years of RTL development experience.
• Advanced RTL design knowledge with VHDL or Verilog/SystemVerilog.
• Basic knowledge of UVM Testbench development.
• Strong communication and presentation skills in English.

Responsibilities

• Develop micro-architecture specifications and design documentation.
• RTL development using VHDL or Verilog/SystemVerilog according to requirements.
• Perform linting, CDC, synthesis and power optimization.
• Identify, select and integrate soft and hard IP.
• Develop timing and power constraints.
• Collaborate with analog design team for mixed-signal designs and with verification team for plans and debugging.
• Collaborate with physical design team to meet timing and power goals.

Skills

RTL Development

VHDL

Verilog/SystemVerilog

UVM

English communication

Tools

Synthesis tools

Place-and-Route

Job description

Summary: Designs advanced digital building blocks for various applications, incl. but not limited to power management, low-power & low-voltage applications.

Responsibilities

• Micro-architecture specification development and design documentation
• RTL development using VHDL or Verilog/System Verilog, according to functional requirements and following design guidelines
• Lint, CDC, Synthesis, & Power Optimization
• Soft and hard IP identification, selection and integration
• Timing and power constraints development
• Collaboration with analog design team for mixed-signal designs
• Collaboration with verification team in verification plan development and debug
• Collaboration with physical design team to close the design on timing and power
• 4 yearsexperience in RTL development
• Advanced knowledge of RTL design using VHDL or Verilog/SystemVerilog
• Basic knowledge of UVM Testbench development
• Strong communication and presentation skills in English

Preferred Qualification

• Knowledge of mixed signal concepts
• Hands-on experience with synthesis and/or place-and-route
• Able to work in a team
• Good problem solving skills and being able to implement solutions autonomously