Full Chip Timing Lead

AMD; Elsene; On-site; EUR 90,000 - 150,000; Full time

Job summary

Advanced Micro Devices, Inc. is seeking a Full Chip Timing Lead for Physical Design to drive timing closure across high-frequency interfaces and CPU/HBM/DDR paths.

You will own SDC work, signoff verification, and collaborate with global CAD teams to optimize the design flow and deliver first-pass silicon success.

Qualifications

• 8+ years in design signoff closure or equivalent experience.
• Timing closure at SoC and block levels with multi-volt considerations.
• Deep knowledge of STA, high-frequency interface closure, and ECO flows.
• Experience with PnR-STA convergence and signoff correlation.

Responsibilities

• Own full chip timing closure and drive improvements.
• Analyze data and provide feedback to PD execution teams.
• Perform SDC analysis and guidance for flow enhancements.
• Collaborate with CAD, PnR, and central methodology teams.

Skills

SoC timing

STA signoff

SDC coding

TCL scripting

Python scripting

Multi-geo work

Automation scripting

Education

Bachelor's or Master's in Computer or Electrical Engineering

Tools

Synopsys

Cadence

Mentor

TileBuilder

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

Full Chip Timing Lead - Physical Design

THE ROLE:

• Drive clock guidance from architecture to PD on toplogy to construction to closure
• As a member of the PD Full Chip STA closure and optimization team, you will work on SoC Full Chip Timing closure which includes high frequency CPU, HBM, DDR, Serdes interfaces. Will be responsible for SDC validation and timing signoff execution with different team members and will work closely with the methodology and CAD teams across various geographies to achieve first pass silicon success.

THE PERSON:

• A successful person in this role would be able to work in a collaborative team environment working with other business units, central methodology team driving the group signoff and solving the critical issues with vendor.
• Strong self-driving ability, should have excellent communication skills (both written and oral)

KEY RESPONSIBILITIES:

• Owns Full chip Timing Closure
• Drive new improvement in closure
• Analysis of data and feedback to PD execution team
• SDC analysis and feedback
• Work with PnR engineer for timing convergence
• Drive the common STA methodology in the business unit
• Work and collaborate with different business units, CAD and central methodology team to drive the requirement
• Automation to refine and improve design signoff requirement and dashboarding
• Ability to organize and present complex technical information in a crisp and concise manner.
• Interact with other PPA (equivalent) teams internal to AMD
• Identify best practices across AMD and industry to update and improve flow/project settings
• To increase the competitiveness of each stage in AMD design flow
• Ability to work with multi-level functional teams across various geographies.
• Highly organized, strong affinity for automation and prioritization.

PREFERRED EXPERIENCE:

• 8+ year or more experience design signoff closure
• Timing closure experience at SoC and block level
• Technical depth in STA, High freq interface closure in hierarchical STA.
• Multi voltage closure
• Timing ECO flow
• Hyperscale, Yield analysis
• PnR and STA signoff correlation drive and convergence
• Strong at SDC coding and debug skills
• Drive new requirements and methodology to aid timing closure at SoC
• Identify the gaps and support flows
• Strong in scripting, Scripting language experience: TCL, Perl, Python, Makefile.
• Drive team towards common requirements and flows
• Experienced in deploying and implementing ML techniques and algorithms in physical design.
• Low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
• Experience with different tools from various vendors - Synopsys, Cadence and Mentor.
• AMD block TileBuilder and experience in lower tech nodes (5/3/2) is a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.