Senior DV Engineer - SoC/IP Verification

Apple Inc.; Melbourne; Hybrid; AUD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Melbourne is seeking a design verification engineer to ensure bug-free first silicon for IP and SoC blocks. You will craft verification methodology, test plans, and scalable environments to validate complex designs.

You will develop verification environments, including stimulus, checkers, assertions, trackers, and coverage metrics, while leveraging LLMs to improve efficiency and quality. Strong SystemVerilog/UVM experience and a 10+ year background are expected.

Qualifications

• BS degree in a technical field with 10+ years in verification.
• Experience with SystemVerilog/UVM and DV methodologies.
• Experience with LLMs for verification is a plus.

Responsibilities

• Study design specification and create test plan.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

OOP

LLMs in verification

Python

Testbench development

Education

Bachelor's degree in technical subject

Tools

SystemVerilog

UVM

Simulation Tools

Job description

Apple Inc. in Melbourne is seeking a design verification engineer to ensure bug-free first silicon for IP and SoC blocks. You will craft verification methodology, test plans, and scalable environments to validate complex designs.

You will develop verification environments, including stimulus, checkers, assertions, trackers, and coverage metrics, while leveraging LLMs to improve efficiency and quality. Strong SystemVerilog/UVM experience and a 10+ year background are expected.