Design Verification Engineer

Apple, Inc.; Melbourne; Hybrid; AUD 110,000 - 150,000; Full time

Job summary

Apple is seeking an outstandingly hardworking design verification engineer to develop pre-silicon verification for IP designs. You will craft test plans, build scalable verification environments, and drive regression analysis using SystemVerilog/UVM and LLMs to improve quality and efficiency.

You will work on first silicon for IP blocks, develop verification plans, and report DV progress with metrics across bugs and coverage. A strong background in DV methodology is required.

Qualifications

• BS degree in a technical subject area.
• 3+ years relevant industry experience.

Responsibilities

• Study design specification and create test plans.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

OOP

SystemVerilog

UVM

Testbench development

LLMs for verification

Power-aware verification

Python/Perl/TCL

PCIe/USB/DDR protocols

Formal verification (plus)

Education

Bachelor's degree in a technical subject

MS degree in a technical subject (preferred)

Tools

Simulation tools

Waveform viewer

Build & run automation

Gate-level simulations

UPF tooling

LLM-assisted verification

Job description

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable.Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Minimum Qualifications

• BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent.

Preferred Qualifications

• MS degree in a technical subject area and relevant industry experience strongly preferred
• Strong knowledge of OOP, SystemVerilog and UVM
• Strong knowledge in developing scalable and portable testbenches
• Proven experience with verification methodologies and tools such as simulators, waveform viewer, build and run automation, coverage collection, and gate-level simulations
• Working experience using LLMs for efficiency and quality
• Experience with power-aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL
• Some experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required
• Knowledge of formal verification methodology is a plus but not required

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.