Lead DV Engineer – Computer Vision Accelerators

Meta; Redmond; On-site; AUD 256,000 - 359,000; Full time

Benefits offered by this job

Equity

Bonus program

Benefits package

Job summary

Meta is hiring a Design Verification Engineer to own verification for accelerators, focusing on computer vision and imaging IPs. The role shapes verification strategy across IPs and builds scalable DV infrastructure across chips and programs, driving high-throughput verification with advanced techniques.

You will collaborate with architects, design, firmware, emulation, and physical design to ensure verification is integrated from the start.

Qualifications

• 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level.
• Has led DV for complex IP or an SoC through tape-out, including owning sign-off.
• Has defined and run verification plans, coverage strategies, and closure metrics across multiple blocks or IPs.
• Has built UVM verification environments from scratch and designed reusable verification components.
• Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification.
• Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows.
• Has led and mentored engineers and coordinated work across teams.

Responsibilities

• Shape architecture and microarchitecture decisions with architects and other teams for verification-aware design.
• Own DV for multiple complex IPs or subsystems from planning through sign-off.
• Define DV strategy across IPs, including simulation, formal, assertions, emulation and UPF verification.
• Design reusable testbench architectures and verification components shared across IPs and SoCs.
• Drive regression management, coverage analytics, and compute-efficient runs across growing designs.
• Identify DV quality gaps and lead initiatives to improve time-to-closure and DV methodologies, including AI-assisted approaches.
• Root-cause failures to RTL, reference models, or FW/SW and propose fixes.

Skills

SystemVerilog

UVM

C/C++

Python

DV infrastructure

Formal verification

SVA

Emulation

UPF (low-power)

Leadership / mentoring

Education

Bachelor's degree in Computer Science / Computer Engineering or related field

Bachelor's degree in Electrical Engineering / Computer Engineering or related field

Tools

Emulation platforms

FPGA prototyping

C/C++ toolchains

Job description

Meta is hiring a Design Verification Engineer to own verification for accelerators, focusing on computer vision and imaging IPs. The role shapes verification strategy across IPs and builds scalable DV infrastructure across chips and programs, driving high-throughput verification with advanced techniques.

You will collaborate with architects, design, firmware, emulation, and physical design to ensure verification is integrated from the start.