Verification Engineer

Motion Recruitment; South Australia; On-site; AUD 100,000 - 120,000; Full time

Job summary

A leading recruitment firm in Australia seeks a Verification Engineer to join a cutting-edge SoC design team in Adelaide. In this role, you will take ownership of verification processes for advanced designs and develop UVM-based test environments. Ideal candidates should have over 5 years of experience in digital design or SoC verification, with strong skills in System Verilog/Verilog and familiarity with industry-standard tools. Enjoy a supportive environment focused on technical excellence and career growth.

Qualifications

• 5+ years of experience in digital design or SoC verification.
• Strong skills in System Verilog/Verilog and UVM methodologies.
• Experience with RTL simulation and debug.
• Hands-on FPGA implementation and debug experience.

Responsibilities

• Take ownership of verification for advanced SoC designs from concept to sign-off.
• Develop and execute UVM-based test environments in SystemVerilog/Verilog.
• Perform RTL simulation, debug, and coverage analysis.
• Collaborate closely with design, architecture, and implementation teams.
• Contribute to the continuous improvement of design and verification processes.

Skills

Digital design experience

SoC verification skills

System Verilog/Verilog proficiency

UVM methodologies knowledge

RTL simulation skills

Debugging experience

Familiarity with Git

Curiosity and proactiveness

Chip implementation knowledge

FPGA implementation experience

Tools

Industry-standard verification tools

Version control tools

Job description

Overview

We are looking for a passionate and talented Verification Engineer to join a cutting-edge SoC design team in Adelaide. You'll work on complex digital and mixed-signal systems that power innovative technologies across multiple industries. If you enjoy solving challenging technical problems, collaborating with brilliant engineers, and seeing your work make a real-world impact - this is the role for you.

What you will be doing

• Take ownership of verification for advanced SoC designs from concept to sign-off.
• Develop and execute UVM-based test environments in SystemVerilog/Verilog.
• Perform RTL simulation, debug, and coverage analysis using industry-standard tools.
• Collaborate closely with design, architecture, and implementation teams.
• Contribute to the continuous improvement of design and verification processes.
• Explore and develop your skills across new technologies and tools.

What you will bring

• 5+ years\' experience in digital design or SoC verification.
• Strong skills in System Verilog/Verilog and UVM methodologies.
• Experience with RTL simulation and debug.
• Familiarity with version control tools such as Git.
• A curious mindset, proactive attitude, and enthusiasm to learn new areas.
• Knowledge of chip implementation, synthesis, and P&R.
• Hands-on FPGA implementation and debug experience.
• Understanding of power and performance optimisation techniques.
• Work with a high-calibre engineering team solving complex design challenges.
• Be part of leading-edge SoC development projects with real global impact.
• Enjoy a supportive and innovative environment that values technical excellence and career growth.