A leading recruitment firm in Australia seeks a Verification Engineer to join a cutting-edge SoC design team in Adelaide. In this role, you will take ownership of verification processes for advanced designs and develop UVM-based test environments. Ideal candidates should have over 5 years of experience in digital design or SoC verification, with strong skills in System Verilog/Verilog and familiarity with industry-standard tools. Enjoy a supportive environment focused on technical excellence and career growth.
Qualifications
5+ years of experience in digital design or SoC verification.
Strong skills in System Verilog/Verilog and UVM methodologies.
Experience with RTL simulation and debug.
Hands-on FPGA implementation and debug experience.
Responsibilities
Take ownership of verification for advanced SoC designs from concept to sign-off.
Develop and execute UVM-based test environments in SystemVerilog/Verilog.
Perform RTL simulation, debug, and coverage analysis.
Collaborate closely with design, architecture, and implementation teams.
Contribute to the continuous improvement of design and verification processes.
Skills
Digital design experience
SoC verification skills
System Verilog/Verilog proficiency
UVM methodologies knowledge
RTL simulation skills
Debugging experience
Familiarity with Git
Curiosity and proactiveness
Chip implementation knowledge
FPGA implementation experience
Tools
Industry-standard verification tools
Version control tools
Job description
A leading recruitment firm in Australia seeks a Verification Engineer to join a cutting-edge SoC design team in Adelaide. In this role, you will take ownership of verification processes for advanced designs and develop UVM-based test environments. Ideal candidates should have over 5 years of experience in digital design or SoC verification, with strong skills in System Verilog/Verilog and familiarity with industry-standard tools. Enjoy a supportive environment focused on technical excellence and career growth.