Design Verification Engineer – SoC Pre-Silicon (SystemVerilog/UVM)

Apple, Inc.; Melbourne; Hybrid; AUD 110,000 - 150,000; Full time

Job summary

Apple is seeking an outstandingly hardworking design verification engineer to develop pre-silicon verification for IP designs. You will craft test plans, build scalable verification environments, and drive regression analysis using SystemVerilog/UVM and LLMs to improve quality and efficiency.

You will work on first silicon for IP blocks, develop verification plans, and report DV progress with metrics across bugs and coverage. A strong background in DV methodology is required.

Qualifications

• BS degree in a technical subject area.
• 3+ years relevant industry experience.

Responsibilities

• Study design specification and create test plans.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Develop and fix failures from regressions, close bugs.
• Use LLMs to do verification efficiently.

Skills

OOP

SystemVerilog

UVM

Testbench development

LLMs for verification

Power-aware verification

Python/Perl/TCL

PCIe/USB/DDR protocols

Formal verification (plus)

Education

Bachelor's degree in a technical subject

MS degree in a technical subject (preferred)

Tools

Simulation tools

Waveform viewer

Build & run automation

Gate-level simulations

UPF tooling

LLM-assisted verification

Job description

Apple is seeking an outstandingly hardworking design verification engineer to develop pre-silicon verification for IP designs. You will craft test plans, build scalable verification environments, and drive regression analysis using SystemVerilog/UVM and LLMs to improve quality and efficiency.

You will work on first silicon for IP blocks, develop verification plans, and report DV progress with metrics across bugs and coverage. A strong background in DV methodology is required.