Senior Physical Design Engineer - High-Performance PHY/SOC

Apple, Inc.; Melbourne; Hybrid; AUD 180,000 - 240,000; Full time

Job summary

Apple in Melbourne, Australia invites applications for a forward‑thinking Physical Design Engineer. You will work across architecture, CAD, timing and logic teams to deliver outstanding PHY designs that power Apple’s products used by millions daily.

You will contribute to RTL-to-GDSII physical design, optimize floor-plans, clock networks and power grids, and drive ECOs and verifications with a strong emphasis on correctness and efficiency. This role demands deep PHY/SoC experience.

Qualifications

• Bachelor's degree in Electrical Engineering with 10+ years of industry experience.
• Experience with high-performance PHY or SoC designs.
• Strong knowledge of physical design concepts and tools.

Responsibilities

• Generate block/chip level constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Perform block level place and route and close the design to meet timing, area and power constraints.
• Generate and Implement ECOs to fix timing, noise and EM IR violations.
• Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies for correct by construction designs.
• Assist in flow development for chip integration.

Education

B.S. in Electrical Engineering

Tools

Power-grid design tools

Place & Route tools

Synthesis tools

STA tools

LVS/DRC debugging tools

Job description

Apple in Melbourne, Australia invites applications for a forward‑thinking Physical Design Engineer. You will work across architecture, CAD, timing and logic teams to deliver outstanding PHY designs that power Apple’s products used by millions daily.

You will contribute to RTL-to-GDSII physical design, optimize floor-plans, clock networks and power grids, and drive ECOs and verifications with a strong emphasis on correctness and efficiency. This role demands deep PHY/SoC experience.