Firmware Engineer — AI ASIC Accelerator

MBR Partners; Dubai; On-site; AED 120,000 - 200,000; Full time

Job summary

A leading tech company in Dubai is seeking an experienced ASIC Firmware Engineer to lay the software foundation for next-generation AI training ASIC. The role involves collaborating with teams to develop secure boot chains, runtime management, and communication protocols. The ideal candidate has over 5 years of embedded firmware experience and a solid background in hardware integration such as PCIe and Ethernet interfaces. Competitive compensation and stimulating projects are offered.

Qualifications

• 5+ years of experience in embedded firmware development on ASIC/SoC or GPU-like accelerators.
• Proven experience with PCIe bringing up, HBM/DDR subsystems or 100G+ Ethernet.
• Strong documentation habits and ability to think across the full stack.

Responsibilities

• Implement secure boot chain and device attestation.
• Bring up clocks, power domains, HBM, PCIe, and high-speed SerDes PHY.
• Configure 400G Ethernet interfaces and coordinate with the network stack.

Skills

Embedded firmware development (C/C++/Rust)

Experience with PCIe bringing up

Clock/power domain configuration

Documentation habits

System thinking

Tools

JTAG debugging tools

Logic analyzers

Job description

ASICFirmwareEngineer.

FirmwareEngineer—AIASICAccelerator

We’relookingforanexperiencedFirmwareEngineertobuildthelow-levelsoftwarefoundationforournext-generationAItrainingASIC.Inthisrole,you’llimplementthesecurebootchain,hardwarebring-upsequences,runtimemanagement,andhostcommunicationprotocolsthatbridgecustomsiliconandAIworkloads.You’llcollaboratewithsiliconarchitects,Linuxdriverengineers,securityteams,andsystemvalidationtodeliverproduction-gradefirmwareforenterpriseAIinfrastructure.

Experiencenecessarytodothefollowing:

• Implementsecurebootchain(BootROM→PBL/SBL→RTOS),deviceattestation,andfieldupdatemechanisms
• Bringupclocks,powerdomains,HBM,PCIe,NoC,andhigh-speedSerDesPHYsonemulation/FPGAandsilicon
• Configure400GEthernetinterfaces(MAC/PCS/FEC)andcoordinatewithnetworkstackforRDMAoffload
• Developruntimeservices:power/thermalcontrol,DVFS,watchdogs,RAS(ECC,crashdumps),errorrecovery
• Designmailboxprotocols,MSI/MSI-Xhandling,andDMAcoordinationwithLinuxdriverteam
• Buildunifiedtelemetryandeventtracingwithsynchronizeddatetimestamps(PTP/PHC)
• Supportmulti-diediscovery,linktraining,andtopologymanagementforchipletscaling

WhatWe’reLookingFor:

• 5+yearsembeddedfirmware(C/C++/Rust)onASIC/SoCorGPU-likeaccelerators
• ProvenexperiencewithPCIebring-up,HBM/DDRsubsystems,or100G+Ethernet—atleastoneisamust
• Hands-onwithclock/powerdomainconfigurationandRASfeatures
• Comfortablewithschematics,registerspecs,JTAG/logicanalyzerdebugging
• Strongdocumentationhabitsandsystemsthinkingacrossthefullstack
• RISC-V/ARM64,TrustZone/TEE,secureprovisioning,orQEMUpre-siliconexperienceisaplus
• Familiarity with requirements traceability is valued