Senior Wireless Verification Architect — SoC & UVM Expert

Apple Inc.; Irvine (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Retirement benefits

RSU stock plan

Employee stock purchase plan

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. is seeking a Senior Wireless Design Verification Engineer in Irvine, CA to lead verification of WiFi SOC components. You will architect UVM testbenches, develop constrained random scenarios, and drive coverage-driven verification across controllers, datapaths, and subsystems.

You will collaborate with multiple teams to define requirements, debug complex issues, and deliver high-quality silicon. Strong SystemVerilog/UVM skills and Python automation are essential for this leadership

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Demonstrated expertise verifying complex digital ASICs with track record of successful silicon tapeouts.
• Deep knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture, verification planning, and coverage-driven methodologies.
• Experience developing verification environments from scratch and bringing up complex designs in simulation.
• Experience with constrained random testing, functional coverage, and assertion-based verification.

Responsibilities

• Lead subsystem-level verification from test planning, environment definition, and design bring-up through feature closure.
• Architect sophisticated UVM testbench environments, infrastructure frameworks, and reusable verification IP with automation capabilities.
• Develop constrained random scenarios for complex protocol, and multi-domain behaviors.
• Lead cross-functional collaboration to define verification requirements, debug complex issues, and drive decisions.
• Drive coverage-driven methodologies, and metric analysis frameworks.

Skills

SystemVerilog

UVM

Python

Verification leadership

Regression infra

Education

BS in Electrical/Computer Engineering

Tools

DPI integration

BFMs

TL modeling

SystemVerilog testbenches

Job description

Apple Inc. is seeking a Senior Wireless Design Verification Engineer in Irvine, CA to lead verification of WiFi SOC components. You will architect UVM testbenches, develop constrained random scenarios, and drive coverage-driven verification across controllers, datapaths, and subsystems.

You will collaborate with multiple teams to define requirements, debug complex issues, and deliver high-quality silicon. Strong SystemVerilog/UVM skills and Python automation are essential for this leadership