Wireless SOC Verification Engineer - AI-Driven, Low-Power

Apple Inc.; Sunnyvale (CA); Presencial; USD 123.000 - 214.000; Jornada completa

Descripción de la vacante

Apple Inc. is seeking a Wireless SOC Design Verification Engineer in Sunnyvale, CA, to own pre-silicon RTL verification across blocks up to the SOC.

You will partner with architects and firmware engineers to build reusable testbenches and verification environments, selecting simulation, formal, or other approaches as needed. The role emphasizes low-power verification with UPF, coverage-driven methodology, and opportunity to grow into broader IP and SOC levels while collaborating on AI-assisted

Formación

• Bachelor's degree required with hands-on verification experience.
• Strong SystemVerilog/Verilog and UVM knowledge.
• Experience with PCIe, bus fabrics, or AHB/AXI in a UVM environment.

Responsabilidades

• Partner with architects and designers to build detailed verification plans from specifications before RTL lands.
• Develop reusable block/IP and subsystem-level UVM testbenches; support IP integration into the SOC.
• Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
• Debug failures, including corner cases, and manage bug tracking through resolution.
• Verify low-power design intent using UPF within your scope.
• Verify end-to-end WiFi and Bluetooth traffic from subsystem to top-level SOC integration.
• Apply formal verification where it fits; contribute to verification methodology.
• Build and improve automated regression flows and contribute to the team’s productivity.
• Explore AI-assisted verification techniques to improve efficiency.

Conocimientos

SystemVerilog

Verilog

UVM

Constrained-random verification

Python

C/C++

Debugging

Educación

Bachelor's degree

Herramientas

JasperGold

UPF

Descripción del empleo

Apple Inc. is seeking a Wireless SOC Design Verification Engineer in Sunnyvale, CA, to own pre-silicon RTL verification across blocks up to the SOC.

You will partner with architects and firmware engineers to build reusable testbenches and verification environments, selecting simulation, formal, or other approaches as needed. The role emphasizes low-power verification with UPF, coverage-driven methodology, and opportunity to grow into broader IP and SOC levels while collaborating on AI-assisted