Video Codec ASIC Design Engineer (H.265/HEVC)

ByteDance; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Job summary

ByteDance is seeking an ASIC Design Engineer for its Video Silicon IP team in the U.S. The role focuses on designing high-performance video codec hardware (ASIC/FPGA) and RTL for multi-standard codecs, with collaboration across architecture, algorithm, and verification groups.

You will implement RTL for codec pipelines, support verification, and ensure timing closure while optimizing area and power. A strong background in SystemVerilog and VLSI concepts is required.

Qualifications

• MS/PhD in Electrical Engineering or related field.
• 2 years of ASIC front-end design as primary RTL owner.
• Proficiency in SystemVerilog RTL design or High level Synthesis (HLS).
• Familiarity with UVM, DPI, and C++.
• Solid understanding of VLSI design concepts: pipelining, clock gating, memory architecture, AXI/APB, SV assertion basics.
• Python scripting for EDA flow automation.

Responsibilities

• Design high-performance, low-power video processing IPs within the Video Silicon IP team.
• Develop RTL for video codec pipeline stages including intra/inter prediction, transform/quantization, entropy coding.
• Collaborate with architecture, algorithm and verification teams to translate specifications into hardware.
• Drive functional correctness with verification using directed/constrained-random UVM test benches; debug RTL coverage.
• Understand synthesis, timing analysis, and CDC/RDC checks; assist floor planning and timing closure.

Skills

SystemVerilog RTL

Verilog/SystemVerilog

UVM

Python scripting

C++ (DPI)

Education

MS/PhD in Electrical Engineering or related field

Tools

UVM/DPI/C++

Job description

ByteDance is seeking an ASIC Design Engineer for its Video Silicon IP team in the U.S. The role focuses on designing high-performance video codec hardware (ASIC/FPGA) and RTL for multi-standard codecs, with collaboration across architecture, algorithm, and verification groups.

You will implement RTL for codec pipelines, support verification, and ensure timing closure while optimizing area and power. A strong background in SystemVerilog and VLSI concepts is required.