Video Codec ASIC Design Engineer Intern

ByteDance; San Jose (CA); Presencial; USD 52.000 - 72.000; A tiempo parcial

Ventajas ofrecidas por este puesto de trabajo

Health insurance

Housing allowance

Paid holidays

Paid sick time

Descripción de la vacante

ByteDance's video silicon IP team offers an internship for engineering students to contribute to high-performance, low-power video encoding and processing hardware (ASIC/FPGA). You will gain hands-on experience across architecture, algorithm, software, firmware and hardware verification while working on industry-leading IP.

The internship emphasizes practical learning, collaboration with architecture, verification teams, and exposure to SystemVerilog, HLS, UVM, SystemC, and Python tasks in a

Formación

• Currently pursuing an undergraduate in computer science/electrical engineering or related technical discipline.
• Knowledge of video codecs.
• Experience with RTL design (SystemVerilog) or High Level Synthesis (HLS).
• Experience with UVM methodology, SystemC, or DPI.
• Good programming skills in Python for task automation.

Responsabilidades

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs. Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.

Conocimientos

Video Codecs

RTL design

SystemVerilog

High Level Synthesis

UVM

SystemC

DPI

Python

Educación

Undergraduate in computer science / electrical engineering

Herramientas

N/A

Descripción del empleo

ByteDance's video silicon IP team offers an internship for engineering students to contribute to high-performance, low-power video encoding and processing hardware (ASIC/FPGA). You will gain hands-on experience across architecture, algorithm, software, firmware and hardware verification while working on industry-leading IP.

The internship emphasizes practical learning, collaboration with architecture, verification teams, and exposure to SystemVerilog, HLS, UVM, SystemC, and Python tasks in a