SoC Video Codec Digital Design Engineer (FPGA/ASIC)

TikTok; San Jose (CA); On-site; USD 162,000 - 317,000; Full time

Benefits offered by this job

Medical, dental & vision insurance

401(k) with company match

Paid time off & parental leave

Job summary

TikTok is hiring a video codec hardware design engineer in San Jose to build scalable FPGA/ASIC accelerators for video encoding and processing. You will shape SoC architecture, implement RTL, and collaborate across verification, backend, and frontend teams to optimize power, timing, and performance.

The role requires Verilog/SystemVerilog mastery, front-end EDA proficiency, and scripting for automation. A strong foundation in digital circuits and NPU-aware thinking is preferred.

Qualifications

• Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or related field.
• 1+ years of experience in digital front-end design (promising candidates with less experience considered).
• Mastery of Verilog/SystemVerilog and solid foundation in digital circuits.
• Proficiency with front-end EDA tools such as Spyglass, Design Compiler, PrimeTime.
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for automation.

Responsibilities

• Architecture design: define SoC top/subsystem architecture and evaluate power, performance, area early in design.
• RTL implementation: write high-quality Verilog/SystemVerilog RTL and document designs.
• Front-End QC: perform Lint, CDC, and RDC checks to ensure code standards and robustness.
• Cross-Functional collaboration: work with Verification, Backend, Mid-end teams for synthesis constraints and timing.
• Low Power: contribute to chip low-power strategies using Clock/Power Gating and UPF flow.

Skills

Verilog/SystemVerilog

Digital front-end design

NPU architecture understanding

SoC/Hardware architecture

Scripting for automation

Education

Bachelor's degree or higher in Microelectronics, ICs, CS or EE

Tools

Spyglass

Design Compiler

PrimeTime

Job description

TikTok is hiring a video codec hardware design engineer in San Jose to build scalable FPGA/ASIC accelerators for video encoding and processing. You will shape SoC architecture, implement RTL, and collaborate across verification, backend, and frontend teams to optimize power, timing, and performance.

The role requires Verilog/SystemVerilog mastery, front-end EDA proficiency, and scripting for automation. A strong foundation in digital circuits and NPU-aware thinking is preferred.