Verification Engineer: Automated HDL Validation

IMC; Chicago (IL); Hybrid; USD 175.000 - 225.000; Vollzeit

Benefits dieser Stelle

Discretionary bonus

Paid leave

Insurance

Zusammenfassung

IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development.

The role requires experience with SystemVerilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance.

Qualifikationen

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• 3+ years of experience verifying complex hardware designs using UVM.
• Experience with industry standard 3rd party EDA tools.
• Experience with regression test automation and tracking.
• Ability to develop system and block level testbenches.
• Understanding of metrics-based verification, tracking and reporting coverage to drive to closure.
• Experience in SystemVerilog/Verilog, and C++.
• Experience with scripting languages.
• Ability to work in a Linux environment.

Aufgaben

• Work in a small and globally distributed team that takes responsibility for the complete solution.
• Collaborate closely with RTL and SW team to validate complex systems.
• Automate verification flow for fast turn‑around time to enable rapid development.
• Use a variety of tools and methods to drive for successful end results.

Kenntnisse

UVM verification

SystemVerilog/Verilog

C++

Scripting

Linux

Regression testing

Testbenches

EDA tools

Metrics-based verification

Ausbildung

Bachelors in Electrical Engineering or Computer Engineering

Tools

3rd party EDA tools

Jobbeschreibung

IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development.

The role requires experience with SystemVerilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance.