IP Verification Engineer — RTL, UVM & Power (Hybrid)

Intel Corporation; Hillsboro (OR); Hybrid; USD 106.000 - 200.000; Vollzeit

Benefits dieser Stelle

Stock bonuses

Health benefits

Retirement plan

Vacation

Zusammenfassung

Intel Corporation in Hillsboro, Oregon invites a seasoned RTL Verification Engineer to join our Logic Design and Validation group. You will build UVM-based testbenches, define verification strategies, and integrate RTL into SoC architectures across multiple projects.

The role emphasizes pre-silicon verification, SystemVerilog assertions, coverage-driven methodologies, and cross‑team collaboration with architecture and physical design.

Qualifikationen

• Experience with Pre-silicon logic validation using SystemVerilog and UVM.
• Experience in Digital design using Verilog and/or SystemVerilog.
• Experience with pre-silicon validation closure across multiple projects.
• Hands-on experience with UVM testbench design, with a focus on reusability and scalability.
• Experience with SystemVerilog Assertions (SVA) for coverage closure.

Aufgaben

• Design & Develop Verification Environments – Build and maintain scalable UVM-based testbenches for mixed-signal CMOS designs.
• Define Verification Strategy – Own verification plans and ensure coverage closure across projects.
• RTL Development & Integration – Develop RTL and integrate into SoC architectures.
• Power Methodology – Develop power verification methodologies for mixed-signal IPs.
• Assertion-Based Verification – Create and apply SVA to strengthen coverage closure.
• Debug & Root Cause Analysis – Identify and resolve pre-silicon failures and drive fixes.

Kenntnisse

RTL verification

UVM testbenches

SystemVerilog

Verilog

Python scripting

Ausbildung

Master's in ECE or related

Bachelor's in ECE or related

Tools

UVM

Verilog

SystemVerilog

UPF (Power)

Jobbeschreibung

Intel Corporation in Hillsboro, Oregon invites a seasoned RTL Verification Engineer to join our Logic Design and Validation group. You will build UVM-based testbenches, define verification strategies, and integrate RTL into SoC architectures across multiple projects.

The role emphasizes pre-silicon verification, SystemVerilog assertions, coverage-driven methodologies, and cross‑team collaboration with architecture and physical design.