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IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development.
The role requires experience with SystemVerilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance.
As a Verification Engineer at IMC, you will be part of the R&D team. You’ll have the opportunity to work on novel solutions to accelerate trading decisions to the technological limit. In addition, you’ll work on forward looking solutions that anticipate future requirements.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full‑time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance.
IMC is a research-driven trading firm where quantitative modeling, machine learning, and engineering shape how modern markets are traded. A stabilizing force in markets since 1989, we provide liquidity across trading venues, delivering the best outcome in value and risk management to investors. Using our own technology and capital, we build proprietary systems and algorithms that operate across global markets. Our researchers, traders, and engineers work as a collective, combining rapid experimentation, advanced infrastructure, and real‑time feedback to turn insight into execution and execution into advantage.