Automation-Focused Verification Engineer (SystemVerilog)

Linuxconfig

Chicago (IL)

Hybrid

USD 175.000 - 225.000

Vollzeit

Vor 4 Tagen
Sei unter den ersten Bewerbenden

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Zusammenfassung

IMC Trading is seeking a Verification Engineer to join its R&D team in a role focusing on accelerating trading decisions through advanced hardware verification. You will collaborate with RTL and software teams to validate complex systems and automate verification flows for rapid development.

Applicants should have a strong background in SystemVerilog/Verilog, C++, Linux, and scripting, with experience in UVM and regression testing.

Qualifikationen

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical field
  • 3+ years of experience verifying complex hardware designs using UVM
  • Experience with industry standard 3rd party EDA tools
  • Experience with regression test automation and tracking
  • Ability to develop system and block level testbenches
  • Understanding of metrics based verification, tracking and reporting coverage to drive to closure
  • Experience in SystemVerilog/Verilog, and C++
  • Experience with scripting languages
  • Ability to work in a Linux environment

Aufgaben

  • Work in a small and globally distributed team that takes responsibility for the complete solution
  • Collaborate closely with RTL and SW team to validate complex systems
  • Automate verification flow for fast turn-around time to enable rapid development
  • Use a variety available tools and methods to drive for successful end results

Kenntnisse

UVM
SystemVerilog/Verilog
C++
Linux
Scripting languages
Regression testing
Testbench development
EDA tools
Collaboration

Ausbildung

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

3rd party EDA tools

Jobbeschreibung

IMC Trading is seeking a Verification Engineer to join its R&D team in a role focusing on accelerating trading decisions through advanced hardware verification. You will collaborate with RTL and software teams to validate complex systems and automate verification flows for rapid development.

Applicants should have a strong background in SystemVerilog/Verilog, C++, Linux, and scripting, with experience in UVM and regression testing.

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