Verification Engineer

Ubitium GmbH; Germany (OH); On-site; USD 80,000 - 100,000; Full time

Job summary

Ubitium GmbH is seeking talented individuals for RTL and system-level verification roles. Candidates should have strong Verilog/SystemVerilog and UVM skills, as well as experience in processor/SoC designs, preferably with RISC-V.

A Master's degree and at least 2 years of hands-on experience are required. The role involves predominantly on-site work with an evolving remote policy.

Qualifications

• Master’s degree or equivalent in a relevant field.
• Minimum 2 years of hands-on experience in a relevant role.
• Strong Verilog/SystemVerilog skills and UVM knowledge.

Responsibilities

• Perform RTL and system-level verification.
• Develop assertions and coverage methodologies.
• Debug and validate processor/SoC designs.

Skills

Verilog/SystemVerilog

UVM

RTL debug

processor/SoC experience

RISC-V experience

Education

Master’s degree or equivalent

Job description

Focus areas include but are not limited to: RTL and system-level verification, UVM, assertions, coverage, debug.

Prospective team members require strong Verilog/SystemVerilog and UVM; RTL debug skills; processor/SoC experience; RISC-V experience preferred.

Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.