Senior RTL Verification Engineer - UVM & SystemVerilog

Entrada Ventures; Palo Alto (CA); Hybrid; USD 160,000 - 220,000; Full time

Job summary

Entrada Ventures is seeking a Senior RTL Verification Engineer to ensure the functionality and quality of complex digital designs across ASIC and FPGA platforms. You will build robust verification environments and drive coverage‑driven verification from planning through closure.

The ideal candidate has deep hands‑on SystemVerilog, UVM, and Python experience, plus familiarity with industry EDA tools and high‑speed interfaces such as PCIe and Ethernet, with a collaborative, detail‑oriented

Qualifications

• Bachelors or Masters in Electrical/Computer Engineering or related field.
• 7+ years in digital design verification.
• Proficiency with SystemVerilog, UVM and Python.
• Experience with industry‑standard EDA tools (VCS, Questa, Xcelium).
• Understanding of AXI/AXI‑S/APB protocols and high‑speed interfaces (PCIe, Ethernet).
• Strong analytical and cross‑functional collaboration skills.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent.
• Create and execute coverage‑driven verification plans aligned with design specs.
• Develop directed and constrained‑random test cases and sequences to validate functionality.
• Analyze simulation results and perform root‑cause analysis with RTL engineers.
• Automate regression testing and enhance verification infrastructure with Python.

Skills

SystemVerilog

UVM

Python

Digital design fundamentals

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Master’s degree (preferred)

Tools

Synopsys VCS

Siemens/Mentor Questa

Cadence Xcelium

Job description

Entrada Ventures is seeking a Senior RTL Verification Engineer to ensure the functionality and quality of complex digital designs across ASIC and FPGA platforms. You will build robust verification environments and drive coverage‑driven verification from planning through closure.

The ideal candidate has deep hands‑on SystemVerilog, UVM, and Python experience, plus familiarity with industry EDA tools and high‑speed interfaces such as PCIe and Ethernet, with a collaborative, detail‑oriented