Design Verification Engineer

Lumicity; United States; Hybrid; USD 80,000 - 250,000; Full time

Job summary

A global technology company is seeking an experienced verification engineer to join their team. In this role, you'll be developing and maintaining SystemVerilog/UVM-based testbenches while working on cutting-edge RISC-V processors. The ideal candidate will have over 10 years of design verification experience, including expertise in CPU micro-architecture and a background in coverage-driven methodologies. This position offers flexible working options across North America.

Qualifications

• 10+ years of design verification experience (5+ years for exceptional candidates).
• Expertise in SystemVerilog and UVM, including testbench development.
• Strong background in CPU micro-architecture verification.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based testbenches.
• Perform functional verification and RTL bug analysis.
• Analyze processor architecture to create effective verification plans.
• Track and close functional coverage and generate reports.
• Contribute to testbench infrastructure and mentor junior engineers.
• Document verification plans and results.

Skills

SystemVerilog

UVM

CPU micro-architecture verification

Python

Perl

Shell scripting

Analytical skills

Communication skills

Documentation skills

Teamwork

Education

BS/MS in Electrical/Computer Engineering or related field

Job description

This range is provided by Lumicity. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$80,000.00/yr - $250,000.00/yr

Role Overview

Join a global team developing and verifying next-generation high-performance RISC-V processors. Collaborate with architects and designers to build robust verification environments, debug complex issues, drive coverage closure, and contribute to the delivery of production-quality CPU IP for markets including AI, automotive, communications, consumer, and data centers.

Important Note

Candidates must be authorized to work in Canada or the United States without requiring visa sponsorship or transfer now or in the future.

• Senior/Staff roles: Flexible (Vancouver, Portland, or fully remote in North America)
• Junior/Intermediate roles: Required to be onsite in either Portland, OR or Vancouver, Canada

Responsibilities

• Develop, enhance, and maintain SystemVerilog/UVM-based testbenches
• Perform functional verification, regression triage, and RTL bug analysis
• Analyze processor architecture and memory subsystems to create effective verification plans
• Track and close functional coverage, generate reports, and resolve issues through all design phases
• Contribute to reusable testbench infrastructure and mentor junior engineers
• Document verification plans, processes, and results

Qualifications

• BS/MS in Electrical/Computer Engineering or related field
• 10+ years of design verification experience (5+ years considered for exceptional candidates in certain locations)
• Expertise in SystemVerilog and UVM, including ground-up testbench development
• Strong background in CPU micro-architecture verification
• Proven experience with coverage-driven and constrained-random methodologies
• Working knowledge of formal verification is a plus
• Proficiency in scripting (Python, Perl, or Shell)
• Excellent analytical, communication, documentation, and teamwork skills
• Initiative and attention to detail

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