Processor Design Engineer

Ubitium GmbH; Germany (OH); On-site; USD 80,000 - 120,000; Full time

Job summary

Ubitium GmbH is seeking prospective team members with experience in areas like Cache, Memory Management Unit, and strong Verilog/SystemVerilog skills. Candidates should have at least a Master’s degree and 2+ years of relevant experience.

This role requires relocation and includes 4 days on-site with 1 day remote work, with the policy subject to change.

Qualifications

• Experience in at least one focus area such as Cache or Memory Management Unit.
• Strong Verilog/SystemVerilog skills.
• RISC-V experience preferred.

Skills

Verilog/SystemVerilog

RISC-V

Education

Master’s degree or equivalent

Job description

Focus areas include but are not limited to: Cache, Memory Management Unit (MMU), Multi-Core & Bus Coherence, Branch Prediction, Debug & Test Structures.

Prospective team members require experience in at least one focus area; strong Verilog/SystemVerilog skills; RISC-V experience preferred.

Master’s degree (or equivalent) and 2+ years of hands‑on experience in a relevant role.

Relocation required. Currently 4 days on-site, 1 day remote. Policy may change.