UVM Verification Architect for SoC & IP

I2Intech LLC; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive compensation

Flexible engagement models

Upskilling opportunities

Job summary

I2Intech LLC is seeking a Design Verification Engineer to build and maintain SystemVerilog/UVM environments for cutting-edge semiconductor IP and SoC designs. You will collaborate with architects and RTL designers to define verification strategy and drive coverage closure across complex blocks.

Ideal candidates have strong SystemVerilog/UVM experience, a solid grounding in digital design and bus protocols, and hands-on use of industry simulators.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• Strong hands-on experience with SystemVerilog and UVM.
• Solid understanding of digital design, bus protocols (AMBA AXI/AHB/APB) and clocking.
• Experience with industry simulators (VCS, Xcelium or Questa) and coverage tools.
• Scripting ability in Python, Perl or Tcl for automation.
• Excellent debugging and communication skills.

Responsibilities

• Develop verification plans from architecture and micro-architecture specifications.
• Build and maintain UVM testbenches, sequences, scoreboards and reference models.
• Drive functional and code coverage closure; write SystemVerilog assertions.
• Debug RTL and testbench failures and work with designers to root-cause issues.
• Run gate-level simulations and power-aware (UPF) simulations where applicable.
• Maintain regression infrastructure and triage nightly results.

Skills

SystemVerilog

UVM

Testbench design

Code coverage

Debugging

Python scripting

Digital design

Clocking & buses

Assertions

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

VCS

Xcelium

Questa

Job description

I2Intech LLC is seeking a Design Verification Engineer to build and maintain SystemVerilog/UVM environments for cutting-edge semiconductor IP and SoC designs. You will collaborate with architects and RTL designers to define verification strategy and drive coverage closure across complex blocks.

Ideal candidates have strong SystemVerilog/UVM experience, a solid grounding in digital design and bus protocols, and hands-on use of industry simulators.