IC Design Verification Architect (UVM/SoC, 802.11)

WinMax Systems Corporation; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology firm in San Jose is looking for a skilled engineer to enhance verification methodologies for unit-level MAC layer simulation. This role involves architecting and implementing test infrastructure and requires expertise in UVM verification environments and knowledge of networking protocols. Candidates should possess a BSCS/BSEE or equivalent with significant experience. This position offers an opportunity to work collaboratively in a dynamic environment with competitive compensation.

Qualifications

• Typically requires a BSCS/BSEE degree and 8 years of related experience.
• An MSCS/MSEE degree and 6 years of related experience is also accepted.
• Experience with establishing and managing coverage metrics is desirable.

Responsibilities

• Establish verification methodology for MAC layer simulation.
• Architect and implement infrastructure for test-benches and APIs.
• Establish metrics and implement tests for functional correctness.

Skills

UVM based verification environments

Knowledge of wired or wireless networking protocols

SystemVerilog

OO programming

Perl

Python

Tcl

C

Education

BSCS/BSEE degree

MSCS/MSEE degree

Tools

Logic simulators from Cadence

Logic simulators from Synopsys

Logic simulators from Mentor

Job description

A leading technology firm in San Jose is looking for a skilled engineer to enhance verification methodologies for unit-level MAC layer simulation. This role involves architecting and implementing test infrastructure and requires expertise in UVM verification environments and knowledge of networking protocols. Candidates should possess a BSCS/BSEE or equivalent with significant experience. This position offers an opportunity to work collaboratively in a dynamic environment with competitive compensation.