Interface IP Verification Engineer - SystemVerilog/UVM

7Rays Semiconductors; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

7Rays Semiconductors is seeking a Design Verification Engineer to join the Interface IP DV team. You will verify IP subsystems, including Ethernet and CPU subsystems, ensuring that architecture requirements are implemented across the hardware-software stack.

This role requires strong expertise in SystemVerilog and UVM, with experience in PCIe/Ethernet protocols and ARM/ARC CPU subsystems. You will collaborate with architects, designers, and external vendors to achieve coverage-driven

Qualifications

• Strong SystemVerilog and UVM expertise.
• Experience with IP/sub-system verification in complex SoCs.
• Knowledge of PCIe and Ethernet protocols.
• Experience with ARM/ARC CPU subsystems.
• Coverage-driven verification methodologies.

Responsibilities

• Own end-to-end verification for one or more IP subsystems including Ethernet and CPU subsystems.
• Develop and maintain UVM/SystemVerilog-based verification environments.
• Validate interoperability of external IPs within the chip architecture.
• Drive coverage closure and verification sign-off by analyzing coverage gaps and stress scenarios.

Skills

SystemVerilog

UVM

IP verification

Job description

7Rays Semiconductors is seeking a Design Verification Engineer to join the Interface IP DV team. You will verify IP subsystems, including Ethernet and CPU subsystems, ensuring that architecture requirements are implemented across the hardware-software stack.

This role requires strong expertise in SystemVerilog and UVM, with experience in PCIe/Ethernet protocols and ARM/ARC CPU subsystems. You will collaborate with architects, designers, and external vendors to achieve coverage-driven