Senior TPU Silicon Design Engineer – ML IP & SoC

Google; Town of Montana (WI); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Job summary

Google is seeking a Senior TPU Design Engineer to contribute to ML IPs for Silicon SoCs. You will define microarchitecture details for ML accelerators, specify data flows and integration needs for subsystems, and drive RTL development with rigorous simulations.

You will also ensure schedules, provide customer support, and participate in synthesis, timing/power estimation, and silicon bring-up across Google’s hardware platforms.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/SystemVerilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development and debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Skills

RTL design

Verilog/SystemVerilog

IP/SoC leadership

ARM-based SoCs

Education

Bachelor's degree in EE/CE/CS

Job description

Google is seeking a Senior TPU Design Engineer to contribute to ML IPs for Silicon SoCs. You will define microarchitecture details for ML accelerators, specify data flows and integration needs for subsystems, and drive RTL development with rigorous simulations.

You will also ensure schedules, provide customer support, and participate in synthesis, timing/power estimation, and silicon bring-up across Google’s hardware platforms.