Senior TPU PCIe Architect & RTL Lead

Socket.dev; Sunnyvale (CA); On-site; USD 199,000 - 270,000; Full time

Job summary

Google in Sunnyvale is seeking a highly experienced PCIe Design Engineer to shape the RTL for next-generation data center accelerators. You will lead PCIe microarchitecture and RTL development, partnering with software and hardware teams to ensure high-performance, power-conscious designs.

The role emphasizes end-to-end RTL lifecycle management, integration with system architects, and post-silicon bring-up to maintain link integrity in AI/ML hardware projects.

Qualifications

• Bachelor's degree or equivalent in EE/CS or related field.
• 10 years ASIC design experience with PCIe focus.
• RTL debugging with Verdi/VCS; scripting in Python/Perl.
• SystemVerilog/Verilog RTL development and microarchitecture.
• PCIe protocol knowledge (LTSSM/TP, data link, PHY).
• Experience with CDC, timing closure or synthesis flows.

Responsibilities

• Lead PCIe microarchitecture and RTL development to meet PPA targets and coding standards.
• Manage the full RTL lifecycle, including documentation and sign-off readiness for lint, CDC and synthesis.
• Partner with system architects to integrate PCIe subsystem for bandwidth, latency and power goals.
• Coordinate with Verification and Physical Design to develop test plans and timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up for link integrity.

Skills

ASIC design experience

RTL debugging

Python/Perl scripting

SystemVerilog/Verilog

PCIe protocol knowledge

CDC/timing closure

Education

Bachelor's degree in EE/CS

Tools

Verdi/VCS

Job description

Google in Sunnyvale is seeking a highly experienced PCIe Design Engineer to shape the RTL for next-generation data center accelerators. You will lead PCIe microarchitecture and RTL development, partnering with software and hardware teams to ensure high-performance, power-conscious designs.

The role emphasizes end-to-end RTL lifecycle management, integration with system architects, and post-silicon bring-up to maintain link integrity in AI/ML hardware projects.