Lead, TPU Compute Verification

Socket.dev; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Bonus target 20%

Job summary

Google's TPU verification management role in Sunnyvale, CA seeks a leader to shape the functional verification for TPU compute designs. You will drive advanced verification infrastructure across subchip, subsystem, and full-chip levels, partnering with design, architecture, and performance teams to ensure architectural compliance and performance goals.

You’ll mentor engineers, guide verification strategies, and deliver robust test plans while advancing silicon bring-up and quality standards for

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of people management experience.

Responsibilities

• Lead the functional verification team for TPU Compute, setting priorities and coaching the team.
• Define verification strategies for complex compute subsystems with cross-functional teams.
• Architect scalable verification environments and flows to improve efficiency.
• Provide technical leadership, conduct code reviews, and establish verification quality standards.
• Influence micro-architectural decisions to improve verification throughput and quality.

Skills

Verification

SystemVerilog

UVM

People management

Leadership

Verification strategy

Education

Bachelor's degree in EE/CE/CS or related field

Master's or PhD in EE/CE/CS (emphasis on computer architecture)

Tools

Industry-standard verification tools

Verification methodologies

Job description

Google's TPU verification management role in Sunnyvale, CA seeks a leader to shape the functional verification for TPU compute designs. You will drive advanced verification infrastructure across subchip, subsystem, and full-chip levels, partnering with design, architecture, and performance teams to ensure architectural compliance and performance goals.

You’ll mentor engineers, guide verification strategies, and deliver robust test plans while advancing silicon bring-up and quality standards for