TPU ASIC Design Verification Manager

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Inc. in Sunnyvale, CA is seeking an ASIC Design Verification Manager to lead verification for TPU designs and shape the future of AI/ML hardware acceleration. You will own key verification components, guide test infrastructure, and partner with front-end design, architecture, and performance teams.

The role emphasizes architectural compliance, high-quality verification, and delivery of scalable TPUs within Google's AI platform. In-person interviews are typically required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Responsibilities

• Lead the functional verification for TPU designs, guiding development of verification infrastructure across subchip, subsystem and full-chip levels.
• Develop comprehensive test plans, write diagnostic code, and build monitors and checkers for quality assurance.

Skills

Verification experience

SystemVerilog

UVM

People management

Education

Bachelor's degree

Master's or PhD preferred

Tools

Python

Perl

Shell

Bash

Job description

Google Inc. in Sunnyvale, CA is seeking an ASIC Design Verification Manager to lead verification for TPU designs and shape the future of AI/ML hardware acceleration. You will own key verification components, guide test infrastructure, and partner with front-end design, architecture, and performance teams.

The role emphasizes architectural compliance, high-quality verification, and delivery of scalable TPUs within Google's AI platform. In-person interviews are typically required.