Senior ASIC Verification Engineer for AI/ML TPU Hardware

Socket.dev; Sunnyvale (CA); On-site; USD 142,000 - 236,000; Full time

Job summary

Google is seeking an ASIC Design Verification Engineer to help shape the future of AI/ML hardware acceleration. You will verify complex digital designs with focus on TPU architecture and its integration in data center AI/ML systems, contributing to scalable silicon solutions powering Google products.

You will join a team delivering high-performance TPUs and accelerators, working through architecture, verification, and silicon bring-up to tape-out in a fast-paced, collaborative environment.

Qualifications

• Bachelor's degree and 8 years of design verification experience.
• Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs.
• Strong knowledge of verification methodologies and debugging.

Responsibilities

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

8 years experience in design verif

RTL verification

SystemVerilog

UVM

Education

Bachelor's degree in EE/CE/CS or related field

MS/PhD preferred in EE/CE/CS with computer architecture focus

Tools

SystemVerilog

UVM

Job description

Google is seeking an ASIC Design Verification Engineer to help shape the future of AI/ML hardware acceleration. You will verify complex digital designs with focus on TPU architecture and its integration in data center AI/ML systems, contributing to scalable silicon solutions powering Google products.

You will join a team delivering high-performance TPUs and accelerators, working through architecture, verification, and silicon bring-up to tape-out in a fast-paced, collaborative environment.