ASIC Design Verification Manager, TPU Compute

Socket.dev; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Benefits

Bonus target 20%

Job summary

Google's TPU verification management role in Sunnyvale, CA seeks a leader to shape the functional verification for TPU compute designs. You will drive advanced verification infrastructure across subchip, subsystem, and full-chip levels, partnering with design, architecture, and performance teams to ensure architectural compliance and performance goals.

You’ll mentor engineers, guide verification strategies, and deliver robust test plans while advancing silicon bring-up and quality standards for

Qualifications

• Bachelor's degree or equivalent practical experience in EE/CE/CS.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of people management experience.

Responsibilities

• Lead the functional verification team for TPU Compute, setting priorities and coaching the team.
• Define verification strategies for complex compute subsystems with cross-functional teams.
• Architect scalable verification environments and flows to improve efficiency.
• Provide technical leadership, conduct code reviews, and establish verification quality standards.
• Influence micro-architectural decisions to improve verification throughput and quality.

Skills

Verification

SystemVerilog

UVM

People management

Leadership

Verification strategy

Education

Bachelor's degree in EE/CE/CS or related field

Master's or PhD in EE/CE/CS (emphasis on computer architecture)

Tools

Industry-standard verification tools

Verification methodologies

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 12 years of experience with industry-standard tools, languages, and methodologies relevant to the development and verification of high-performance silicon.
• Experience leading verification efforts of complex SoC projects, involving compute subsystems for AI/ML accelerators.
• Experience mentoring junior engineers and establishing verification quality standards with excellent investigative and communication skills.
• Proven record of managing verification planning for SoCs, from architecture definition to silicon bring-up.
• Ability to influence cross-functional teams (architecture, design, power, emulation, software) to optimize verification efficiency and product quality.

About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at the subchip, subsystem, and full-chip levels. This includes developing comprehensive test plans, writing diagnostic codes, and building monitors and checkers to ensure quality assurance.

Additionally, you will collaborate closely with front-end design, architecture, and performance teams. By analyzing coverage across multiple dimensions, you will guarantee architectural compliance, ensure functional correctness, and drive your team to meet critical performance goals.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
• Define and drive the execution of comprehensive verification strategies for complex compute subsystems, working with cross-functional design, architecture and power teams to achieve architectural compliance and alignment with performance and power goal.
• Architect scalable, reusable verification environments and flows, driving the adoption of industry-leading methodologies to improve efficiency across the team.
• Provide technical leadership and mentorship to junior engineers, drive code reviews, establish verification quality standards, and guide cross-functional efforts for silicon bring-up.
• Partner with architects and design leads to influence micro-architectural decisions to improve verification throughput and overall quality.