Senior Staff TPU Performance Co-Design Engineer

Google; Town of Montana (WI); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google seeks a Senior Staff Performance Co-design Engineer on the TPU Chip Architecture team in Sunnyvale, CA. You will shape the hardware/software stack for AI/ML acceleration, focusing on performance modeling, verification, and scalable TPU architectures.

You'll lead cross-functional collaboration across research, software, and hardware groups, drive long-term architectural roadmaps, and help translate ML research into production-grade accelerators powering Google's large-scale AI workloads.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field is required.
• 12+ years of experience in computer architecture, chip architecture, or hardware-software co-design.
• Experience developing systems for performance modeling, simulation, or system analysis.

Responsibilities

• Define and drive the technical roadmap and architecture for the hardware/software stack, ensuring unparalleled performance for the training and serving of large ML models.
• Act as the technical liaison between advanced research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
• Architect and oversee the development of next-generation configurable simulation frameworks and cycle-accurate performance models, setting the standard for how the organization evaluates complex micro-architectural decisions.
• Advocate system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements.
• Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence broad organizational strategy and transition paradigm-shifting concepts into production.

Skills

Performance modeling

System analysis

Stakeholder alignment

Education

Bachelor's degree in EE/CE/CS or related

Tools

PyTorch

TensorFlow

Simulation tools

Cycle-accurate models

Job description

Google seeks a Senior Staff Performance Co-design Engineer on the TPU Chip Architecture team in Sunnyvale, CA. You will shape the hardware/software stack for AI/ML acceleration, focusing on performance modeling, verification, and scalable TPU architectures.

You'll lead cross-functional collaboration across research, software, and hardware groups, drive long-term architectural roadmaps, and help translate ML research into production-grade accelerators powering Google's large-scale AI workloads.