Senior ASIC Power Engineer - TPU Power & Architecture Lead

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking an experienced Power Architect to shape the future of AI/ML hardware acceleration, focusing on TPU power design and verification of complex digital designs within AI/ML-driven systems.

You will drive power efficiency for TPU designs, build robust models, and propose optimization techniques while collaborating with software and hardware teams to meet dynamic power targets.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, related field, or equivalent practical experience.
• 10 years of experience in design or architecture (logic design, power architecture, performance, or SoC design).
• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Responsibilities

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Be the technical lead of an experienced power team. Own the execution and delivery of complex technical projects end to end.

Skills

Power design

Power modeling

SoC design

Chip-wide power management

Technical leadership

Project ownership

Power optimization techniques

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science

Master's degree or PhD in Electrical Engineering / Computer Engineering or Computer Science

Job description

Google is seeking an experienced Power Architect to shape the future of AI/ML hardware acceleration, focusing on TPU power design and verification of complex digital designs within AI/ML-driven systems.

You will drive power efficiency for TPU designs, build robust models, and propose optimization techniques while collaborating with software and hardware teams to meet dynamic power targets.