Top-Level SoC Physical Design Engineer — Drive Tapeout

Apple Inc.; Beaverton (OR); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon seeks an experienced chip design professional to drive full-flow ASIC/SoC implementation from netlist to tapeout. You will partner with FE and physical design teams to set goals, guidelines, and milestones for place and route, timing, and IP integration.

Responsibilities include floorplanning, power distribution, global timing, and multi‑domain convergence for large designs (>20M gates) at >1GHz, using sub‑45nm tech. BS plus 10+ years required.

Qualifications

• BS degree in a relevant field and 10+ years of industry experience.
• Strong expertise in ASIC/SoC physical design, floorplanning, and IP integration.
• Experience with multi-VA and timing closure across >20M gates.
• Knowledge of CAD tools and verification flows for physical design.

Responsibilities

• Collaborate with FE and physical design teams to drive architecture and physical implementation.
• Lead place and route activities, set milestones, and manage dependencies.
• Resolve design and flow issues in physical design and drive IP requirements.
• Ensure timing, power, and thermal convergence for large SoC designs.

Skills

ASIC/SoC design

Physical design

Floorplanning

P&R (Place & Route)

Timing analysis

Power integrity

IP integration

Education

Bachelor's degree

Tools

Floorplanning tools

P&R tools

CAD tools

Job description

Apple Inc. in Beaverton, Oregon seeks an experienced chip design professional to drive full-flow ASIC/SoC implementation from netlist to tapeout. You will partner with FE and physical design teams to set goals, guidelines, and milestones for place and route, timing, and IP integration.

Responsibilities include floorplanning, power distribution, global timing, and multi‑domain convergence for large designs (>20M gates) at >1GHz, using sub‑45nm tech. BS plus 10+ years required.