Entry-Level SoC Physical Design Engineer

Apple; Richmond (VA); Remote; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health insurance

401(k) with company match

Paid vacation

Professional development opportunities

Job summary

Apple is seeking an experienced SoC physical design engineer in the United States to drive the full physical design flow from netlist to tape-out. You will coordinate with design and verification teams to deliver high-performance silicon, handling floorplanning, clock and power planning, and hard-IP tight integration.

Responsibilities include managing voltage/clock domain issues, ESD, and power distribution while guiding layout rule checks, timing, and real-time process monitoring for

Qualifications

• Strong experience with all phases of ASIC design: floorplanning, clock and power planning, interface planning, and hard-IP integration.
• Proficiency in handling SoC-level challenges such as voltage and clock domain management, ESD, handshake logic, and power-distribution strategy.
• Knowledge of modern design flow, timing and STA tools, and real-time layout verification.
• Experience with large-scale SoC designs (>20M gates) at high frequencies (>1GHz) using advanced sub-45nm technology.
• Familiarity with design rule compliance for yield, manufacturability, multi-Vt, and thermal management.
• Expertise in floorplanning tools (e.g., PowerSynth, FlowDesigner), place-and-route streams and timing back-checking.
• Strong communication skills to collaborate closely with front-end and layout teams.
• 2+ years of industry experience in SoC physical design.

Responsibilities

• Execute the SoC physical design from netlist to tape-out, collaborating with design and verification teams to deliver high-performance, manufacturable silicon.
• Floorplanning, clock tree synthesis, power delivery design, sign-off planning, I/O planning, and hard-IP integration.
• Manage standard SoC issues such as voltage and clock domain crossing, ESR, ESD, handshaking, and power-distribution network coordination.
• Work with the design and layout teams to drive layout rule checks, timing verification, and real-time process monitoring.
• Plan and drive a complete SoC layout from both internal and external IP, making key decisions on IP placement, routing, and optimization.
• Design and optimize large SoC blocks (>20M gates) running above 1GHz with sub-45nm process nodes.
• Resolve design issues, provide solutions, and drive execution while tracking progress.

Skills

ASIC design

Floorplanning

Clock & power planning

Hard-IP integration

Timing verification

Layout verification

IP placement & routing

Communication

Tools

PowerSynth

FlowDesigner

Place-and-Route

Timing back-checking

STA tools

Job description

Apple is seeking an experienced SoC physical design engineer in the United States to drive the full physical design flow from netlist to tape-out. You will coordinate with design and verification teams to deliver high-performance silicon, handling floorplanning, clock and power planning, and hard-IP tight integration.

Responsibilities include managing voltage/clock domain issues, ESD, and power distribution while guiding layout rule checks, timing, and real-time process monitoring for