Lead Physical Design Engineer, High-Performance PHY/SOC

Apple, Inc.; Beaverton (OR); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple, Inc. in Beaverton, Oregon seeks an experienced Physical Design Engineer to drive high-performance PHY designs from RTL to GDSII.

You will collaborate across architecture, CAD, timing and logic teams to deliver challenging, leading-edge designs that affect millions of Apple customers daily. You will generate constraints, floorplans, and RO measures, perform place-and-route, and implement ECOs while ensuring timing, area and power targets are met.

Qualifications

• Bachelor's degree in Electrical Engineering required.
• Minimum 10 years of relevant industry experience or equivalent.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Perform block level place and route and meet timing, area and power constraints.
• Generate and implement ECOs to fix timing, noise and EM/IR violations.
• Run physical design verification flow and provide guidance to fix LVS/DRC issues.
• Contribute to CAD and physical design methodologies for correct-by-construction designs.
• Assist flow development for chip integration.

Skills

Physical Design

Floorplanning

Place & Route

Verilog

Perl/Tcl

LVS/DRC

Education

Bachelor's of Science in Electrical Engineering

Job description

Apple, Inc. in Beaverton, Oregon seeks an experienced Physical Design Engineer to drive high-performance PHY designs from RTL to GDSII.

You will collaborate across architecture, CAD, timing and logic teams to deliver challenging, leading-edge designs that affect millions of Apple customers daily. You will generate constraints, floorplans, and RO measures, perform place-and-route, and implement ECOs while ensuring timing, area and power targets are met.