Senior SoC Physical Design Lead (Top-Level)

Apple, Inc.; Beaverton (OR); On-site; USD 165,000 - 210,000; Full time

Job summary

Apple, Inc. in Beaverton, Oregon seeks an experienced chip design engineer to deliver complete chip design from netlist to tapeout in a highly visible role.

You will collaborate with FE and physical design teams to define architecture, drive floorplanning, clock/power distribution, IP integration, and manage place and route, timing convergence, and issue resolution. Candidates should have a BS and 10+ years in ASIC design with strong CAD tool experience and a track record on large SoCs (>20M

Qualifications

• BS degree and 10+ years in chip design
• Experience with ASIC integration and IP
• Familiar with floorplanning, clock/power distribution, and physical convergence

Responsibilities

• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
• Collaborate with the physical design team to drive methodologies and best practices, establish guidelines, and track progress.
• Be the focal point for place and route, coordinating among P&R engineers, setting milestones, and planning short/long-term work.
• Resolve design and flow issues related to physical design and drive solutions.

Skills

Chip design

Physical design

Floorplanning

Top-down design

Education

Bachelor of Science in Electrical Engineering or equivalent

Tools

CAD tools

Floorplanning tools

Timing verification tools

Job description

Apple, Inc. in Beaverton, Oregon seeks an experienced chip design engineer to deliver complete chip design from netlist to tapeout in a highly visible role.

You will collaborate with FE and physical design teams to define architecture, drive floorplanning, clock/power distribution, IP integration, and manage place and route, timing convergence, and issue resolution. Candidates should have a BS and 10+ years in ASIC design with strong CAD tool experience and a track record on large SoCs (>20M