Senior SoC Top-Level Physical Design Engineer

Apple, Inc.; Seattle (WA); Sur place; USD 175 000 - 309 000; Plein temps

Avantages offerts par ce poste

Medical coverage

Dental coverage

Stock programs

Tuition reimbursement

Résumé du poste

Apple in Seattle, WA is seeking a senior hardware engineer to own end-to-end chip design from netlist to tapeout. The role focuses on driving physical design, floorplanning, and IP integration across multiple teams.

You will work with the FE and physical design teams to set milestones and ensure robust design convergence. The position requires a BS with 10+ years of industry experience, deep knowledge of ASIC integration, and experience with large SoCs.

Qualifications

• Minimum BS and 10+ years of relevant industry experience.
• Familiar with ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
• Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.

Responsabilités

• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
• Drive place and route, set goals and milestones, plan short and long-term work, and coordinate with top, STA, and block place and route teams.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.

Connaissances

ASIC integration

Floorplanning

Clock distribution

Power distribution

IP integration

SoC design

Formation

Bachelor's degree

Outils

Floorplanning tools

P&R flows

Timing verification

CAD tools

Description du poste

Apple in Seattle, WA is seeking a senior hardware engineer to own end-to-end chip design from netlist to tapeout. The role focuses on driving physical design, floorplanning, and IP integration across multiple teams.

You will work with the FE and physical design teams to set milestones and ensure robust design convergence. The position requires a BS with 10+ years of industry experience, deep knowledge of ASIC integration, and experience with large SoCs.