Entry-Level SoC Physical Design Engineer

Apple; Cheyenne (WY); On-site; USD 27,552 - 41,328; Full time

Job summary

Apple in Cheyenne, USA, is seeking a SoC Physical Design Engineer responsible for executing complete chip design from netlist to tapeout. The role demands strong experience in floorplanning, clock and power routing, timing closure, and physical and electrical checks.

You will work with a cross-functional team to ensure design integrity and timely tapeout, contributing to Apple gear. Bachelor degree required, with 2+ years in relevant industry experience.

Qualifications

• Bachelor degree and at least 2+ years of relevant industry experience.
• Experience with floorplanning, clocking and power routing, timing closure, and physical/electrical checks.
• Experience with hardware design and integration.
• Familiarity with industry-standard design flows and verification steps.

Responsibilities

• Collaborate with the FE team to understand chip design and drive practical considerations throughout the tapeout process.
• Coordinate with the physical design team to optimize real-layout work, enforce rules, drive execution, and track progress.
• Bridge design and layout groups, set targets, plan short- and long-term work, and manage dependencies across areas like top, STA, blocks, and routing.
• Resolve design and flow issues related to physical design, identify alternative approaches, and push to completion.

Skills

Industry experience

Floorplanning

Timing analysis

Physical design

Education

Bachelor Degree

Tools

EDA tools

Job description

Apple in Cheyenne, USA, is seeking a SoC Physical Design Engineer responsible for executing complete chip design from netlist to tapeout. The role demands strong experience in floorplanning, clock and power routing, timing closure, and physical and electrical checks.

You will work with a cross-functional team to ensure design integrity and timely tapeout, contributing to Apple gear. Bachelor degree required, with 2+ years in relevant industry experience.