SoC Physical Design & Timing Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon is seeking a skilled physical design engineer to drive partition-level implementation for a complex SOC. You will collaborate with the logic team from early architecture through netlist to GDS2, ensuring timely delivery and signoff.

The role requires sub-10nm experience, large SOC work, and robust proficiency with standard EDA tools to meet aggressive die-size and performance goals.

Qualifications

• BS degree required and 3+ years of hardware experience.
• Partition level P&R experience including floorplanning.
• Clock and power distribution experience.
• Timing closure and physical verification experience.
• Experience with large SOC designs (>20M gates) at frequencies >1GHz.
• Experience with sub-10nm technology nodes.
• Familiar with industry-standard EDA tools.

Responsibilities

• Collaborate with logic design to define partition architecture early.
• Implement netlist to GDS2 for partitions meeting schedule.
• Perform timing, physical and electrical verification and drive signoff.
• Identify and fix physical design issues and drive execution.

Skills

Partition P&R

Floorplanning

Timing closure

Physical verification

Electrical verification

SOC design

Sub-10nm

EDA tools

Education

Bachelor's degree

Tools

Industry standard tools

Job description

Apple Inc. in Beaverton, Oregon is seeking a skilled physical design engineer to drive partition-level implementation for a complex SOC. You will collaborate with the logic team from early architecture through netlist to GDS2, ensuring timely delivery and signoff.

The role requires sub-10nm experience, large SOC work, and robust proficiency with standard EDA tools to meet aggressive die-size and performance goals.