Cellular SoC Static Timing Analysis Engineer

Apple; San Diego (CA); On-site; USD 171,600 - 302,200; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Retirement benefits

Discounted products and free services

Educational reimbursement

Job summary

A leading technology company in San Diego seeks an experienced STA Engineer to perform static timing analysis and collaborate with design teams. Candidates should have a BS and over 10 years of experience in ASIC timing constraints, as well as expertise in scripting languages such as Tcl and Python. This role offers an attractive salary range between $171,600 to $302,200, alongside various employee benefits and stock options. Join us to help innovate new technologies and be part of a world-class modem team.

Qualifications

• BS degree with 10+ years of relevant experience.
• Expertise in ASIC timing constraints and timing closure.
• Hands-on skills in scripting languages (Tcl and Python).

Responsibilities

• Perform static timing analysis across multiple corners and modes.
• Collaborate with design teams to resolve timing issues.
• Develop automation scripts to streamline analysis and reporting.

Skills

Timing analysis

Static timing analysis

Tcl scripting

Python scripting

Collaboration skills

Education

BS in relevant field

MS in relevant field

Tools

Synopsys PrimeTime

Synopsys CA

Job description

Overview

Summary Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, designed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple’s custom silicon. You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you’ll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?

Responsibilities

• As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple corners and modes using tools like Synopsys PrimeTime.
• The role includes maintaining and validating SDC constraints, collaborating closely with RTL, synthesis, and physical design teams to resolve timing issues.
• Own STA sign-off for block and chip level including custom timing checks. Develop automation scripts in Tcl or Python to streamline analysis and reporting, prepare sign-off quality constraints, and ensure the design meets all performance and reliability targets before tape-out.
• Own STA sign-off for block and chip level including custom timing checks.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.
• Hands-on experience in ASIC timing constraints generation and timing closure.
• Expertise in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
• Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing.
• Strong background in Constraint analysis and debug, using industry standard tools such as Synopsys CA (Constraint Analyzer).
• Knowledge of timing corners/modes, process variations and signal integrity related issues.
• Hands on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl/Python).
• Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of diverse groups (e.g. digital design, DFT, physical design, etc.).

Preferred Qualifications

• MS and 8+ years of relevant industry experience.
• Understand and implement improving existing methodologies and flows. Experience in reducing the number of timing signoff corners by merging different timing modes is highly desired.
• Solid understanding of low-power techniques including clock gating, power gating and multi-voltage designs.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $171,600 and $302,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple accepts applications to this posting on an ongoing basis.