Timing Methodology Engineer – SOC & 3D IC Signoff

Broadcom Inc.; Wayne (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401K with company matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

paid holidays

paid sick leave and vacation

Job summary

Broadcom Inc. is seeking an experienced engineer to advance timing sign-off methodologies for SOC and 3D/2.5D IC design. The role requires ownership of timing signoff and collaboration across teams in a fast-paced project environment.

You will deploy methodologies, lead EDA flow with Primetime, Tempus and Innovus, and contribute to silicon technology yield and testability improvements.

Qualifications

• BS degree in EE/CS with 12+ years of industry experience or MS/PhD with 10+ years.
• Strong hands-on experience in Timing Signoff methodology development and ownership.
• Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
• Experience with statistical data analysis and modeling.
• Experience with silicon technologies, testability and yield.
• Experience with industry standard STA tools such as Primetime and Tempus.
• Proficient in scripting: TCL, Python, Perl, and Unix shell.
• Excellent communication, coordination and problem-solving abilities.

Responsibilities

• Develop and deploy timing signoff methodologies for advanced technology nodes.
• Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.
• Participate and lead in EDA flow development for Primetime, Tempus & Innovus.

Skills

Timing signoff ownership

Strong communication

Multitasking & context switching

Team player

Education

BS EE/CS +12+ years

MS/PhD EE/CS +10+ years

Tools

Primetime

Tempus

Innovus

TCL scripting

Python

Perl

Unix shell

Job description

Broadcom Inc. is seeking an experienced engineer to advance timing sign-off methodologies for SOC and 3D/2.5D IC design. The role requires ownership of timing signoff and collaboration across teams in a fast-paced project environment.

You will deploy methodologies, lead EDA flow with Primetime, Tempus and Innovus, and contribute to silicon technology yield and testability improvements.