Senior SoC Timing & Sign-Off Engineer | MMMC, HBM

Micron Technology; Folsom (CA); On-site; USD 198,000 - 337,000; Full time

Job summary

Micron Technology, a world leader in memory and storage, seeks an experienced Static Timing Analysis (STA) Engineer to own chip‑level timing sign‑off within the Heterogeneous Integration Group. You will collaborate with RTL, physical design, DFT, and product teams to ensure timing integrity from RTL through tape‑out, and develop sign‑off artifacts, constraints, and automation.

This senior role emphasizes hands‑on timing, constraint authoring, automation with Python and Tcl, and MMMC timing

Qualifications

• 10+ years of hands‑on experience owning chip‑level static timing analysis and full timing sign‑off on multiple tapes‑outs at 5nm or below.
• Deep expertise with industry‑standard STA tools such as PrimeTime and/or Tempus.
• Proven ability to develop and manage complex SDC constraints for large SOC with multiple clock/power domains.

Responsibilities

• Own end‑to‑end chip‑level static timing analysis and sign‑off across checks, modes, corners, and voltage/temperature conditions.
• Develop, maintain, and validate sign‑off quality SDCs for clocks, resets, HBM interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full‑chip levels through critical path analysis and ECOs with Physical Design.
• Perform MMMC analysis including clock domain crossing timing and on‑chip variation.
• Lead SI and crosstalk analysis and collaborate with PD on mitigation strategies.
• Build and maintain STA automation and reporting using Python and Tcl for sign‑off readiness.
• Conduct post‑silicon timing correlation and define organization‑wide sign‑off methodologies and dashboards.
• Mentor engineers and collaborate with RTL, Physical Build, Verification, and Test teams to ensure timing requirements are met.

Skills

Chip timing sign-off

PrimeTime

Cadence Tempus

SDC constraint development

Python scripting

Tcl scripting

MMM timing analysis

Multi-domain timing

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Micron Technology, a world leader in memory and storage, seeks an experienced Static Timing Analysis (STA) Engineer to own chip‑level timing sign‑off within the Heterogeneous Integration Group. You will collaborate with RTL, physical design, DFT, and product teams to ensure timing integrity from RTL through tape‑out, and develop sign‑off artifacts, constraints, and automation.

This senior role emphasizes hands‑on timing, constraint authoring, automation with Python and Tcl, and MMMC timing