Senior Timing & Sign-Off Engineer, 2nm+

AMD; San Jose (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

AMD in San Jose is seeking a senior professional to define, develop, and drive timing methodologies across the Adaptive and Embedded Computing Group. You will collaborate with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA, addressing 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs.

The role emphasizes optimizing power, performance, and area while meeting schedules and costs; you will convert

Qualifications

• Experience in custom/physical design and sign-off.
• Proficiency with PD/analysis/sign-off tools.
• Experience with FPGA implementation tools.
• Strong communication and collaboration abilities.
• Programming skills in Python, Perl, or Tcl.

Responsibilities

• Define, develop, and drive timing and power methodologies for advanced process nodes.
• Collaborate with implementation and sign-off teams.
• Work with CAD, power integrity, foundry, and EDA vendors on margins and risk mitigation.

Skills

Custom/physical design

Sign-off engineering

PD/analysis/tools

FPGA tools

Communication

Programming: Python/Perl/Tcl

Collaboration

Education

Bachelor's or Master's in Computer or Electrical Engineering

Tools

Physical design tools

Sign-off tools

FPGA implementation tools

Job description

AMD in San Jose is seeking a senior professional to define, develop, and drive timing methodologies across the Adaptive and Embedded Computing Group. You will collaborate with architecture, product planning, process, design, and product engineering teams to realize silicon solutions with best-in-class PPA, addressing 2nm and beyond on monolithic and 2.5/3DIC adaptive SOCs and FPGAs.

The role emphasizes optimizing power, performance, and area while meeting schedules and costs; you will convert