Senior SoC STA Architect: MMMC Timing Sign-off

Micron Technology; Richardson (TX); On-site; USD 198,000 - 337,000; Full time

Job summary

Micron Technology's Heterogeneous Integration Group seeks a senior STA engineer to own chip-level timing sign-off for next-generation die. You will collaborate with RTL, physical design, DFT, verification and product teams to ensure timing integrity from design through tape-out.

You will develop and validate SDCs for clocks, HBMs, and configuration logic, drive timing closure across blocks and full-chip levels, and mentor junior engineers while building reusable timing methodologies and

Qualifications

• 10+ years hands-on experience owning chip-level static timing analysis and full timing sign-off.
• Expert understanding of MMMC analysis including OCV/AOCV/POCV.
• Proficiency in developing and managing complex hierarchical SDC constraints for large SoCs.

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across checks, modes, corners, and voltage/temperature conditions.
• Develop, maintain, and validate sign-off quality SDCs for clocks, resets, HBMs interfaces, DFT, and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, ECOs, and collaboration with physical design.
• Perform MMMC analysis including clock domain crossing timing and on-chip variation.
• Lead signal integrity and crosstalk analysis and partner with physical design on mitigation strategies.
• Build and maintain STA automation and flows using Python and Tcl for reporting and readiness.
• Conduct post-silicon timing correlation and define organization-wide STA methods and sign-off gates.
• Mentor engineers and collaborate with RTL Build, Verification, Build for Test, Product Engineering and Test teams.

Skills

Chip-level STA ownership

Python scripting

Tcl scripting

Leadership

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Micron Technology's Heterogeneous Integration Group seeks a senior STA engineer to own chip-level timing sign-off for next-generation die. You will collaborate with RTL, physical design, DFT, verification and product teams to ensure timing integrity from design through tape-out.

You will develop and validate SDCs for clocks, HBMs, and configuration logic, drive timing closure across blocks and full-chip levels, and mentor junior engineers while building reusable timing methodologies and