Test Engineer (DFT/ATE) — Edge Silicon

Efficient Computer; Arizona City (AZ); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

401K match

Equity program

Paid parental leave

Flexible work arrangements

Job summary

Efficient Computer is seeking a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. Sit in the intersection of Hardware Engineering and Supply Chain, owning test engineering across multiple active chip programs.

You will work with external design partners and OSAT suppliers to define, implement, and optimize DFT strategy, ATPG patterns, ATE programs, and test flows, including wafer probe, final test, and bin sort.

Qualifications

• 5+ years of semiconductor test engineering experience in fabless or IDM
• Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan
• Experience generating and validating STIL patterns and working with test pattern delivery packages
• ATE test program development experience on Advantest or Teradyne platforms
• Experience supporting wafer probe and final test at OSAT/test house, including load board bringup
• Familiarity with power sequencing requirements and DFT entry flows for ATE test program development
• Ability to work with external design partners and OSAT suppliers to coordinate pattern delivery and test execution
• Strong written and verbal communication skills across multiple time zones

Responsibilities

• Define and execute DFT strategy for each chip program with external partners
• Generate ATPG patterns, including scan, MBIST, JTAG, and embedded memory
• Develop and maintain STIL and PDL for ATE execution
• Drive DFT sign-off and resolve pattern issues with partners
• Support pattern generation including power-up/down sequences and test mode init
• Define power rail sequencing requirements for safe bringup
• Develop and debug ATE programs on Advantest/Teradyne
• Execute first silicon bringup with hardware engineers and OSAT
• Characterize device behavior across voltage, temp, freq
• Coordinate with test partners on load board bring-up and validation
• Manage test flows: wafer probe, final test, bin sort
• Optimize test time and pattern flow to minimize power cycles
• Interface with OSAT and test houses as primary test engineering contact
• Coordinate test program handoff, documentation, and acceptance criteria
• Track yield data, escalate anomalies, drive corrective actions
• Support die traceability and OTP programming in production
• Coordinate capacity planning with supply chain and operations
• Own test engineering across multiple programs
• Build scalable test infra and documentation for future programs
• Contribute to DFT reviews, tapeout checklists, and test escape analysis
• Help mature internal test capabilities over time

Skills

5+ years semiconductor test

Hands-on DFT

ATPG/MBIST/JTAG

ATE test programs

external supplier collaboration

communication across time zones

Tools

Advantest

Teradyne

Job description

Efficient Computer is seeking a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. Sit in the intersection of Hardware Engineering and Supply Chain, owning test engineering across multiple active chip programs.

You will work with external design partners and OSAT suppliers to define, implement, and optimize DFT strategy, ATPG patterns, ATE programs, and test flows, including wafer probe, final test, and bin sort.