Test Engineer

Efficient Computer; Arizona City (AZ); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

401K match

Equity program

Paid parental leave

Flexible work arrangements

Job summary

Efficient Computer is seeking a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. Sit in the intersection of Hardware Engineering and Supply Chain, owning test engineering across multiple active chip programs.

You will work with external design partners and OSAT suppliers to define, implement, and optimize DFT strategy, ATPG patterns, ATE programs, and test flows, including wafer probe, final test, and bin sort.

Qualifications

• 5+ years of semiconductor test engineering experience in fabless or IDM
• Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan
• Experience generating and validating STIL patterns and working with test pattern delivery packages
• ATE test program development experience on Advantest or Teradyne platforms
• Experience supporting wafer probe and final test at OSAT/test house, including load board bringup
• Familiarity with power sequencing requirements and DFT entry flows for ATE test program development
• Ability to work with external design partners and OSAT suppliers to coordinate pattern delivery and test execution
• Strong written and verbal communication skills across multiple time zones

Responsibilities

• Define and execute DFT strategy for each chip program with external partners
• Generate ATPG patterns, including scan, MBIST, JTAG, and embedded memory
• Develop and maintain STIL and PDL for ATE execution
• Drive DFT sign-off and resolve pattern issues with partners
• Support pattern generation including power-up/down sequences and test mode init
• Define power rail sequencing requirements for safe bringup
• Develop and debug ATE programs on Advantest/Teradyne
• Execute first silicon bringup with hardware engineers and OSAT
• Characterize device behavior across voltage, temp, freq
• Coordinate with test partners on load board bring-up and validation
• Manage test flows: wafer probe, final test, bin sort
• Optimize test time and pattern flow to minimize power cycles
• Interface with OSAT and test houses as primary test engineering contact
• Coordinate test program handoff, documentation, and acceptance criteria
• Track yield data, escalate anomalies, drive corrective actions
• Support die traceability and OTP programming in production
• Coordinate capacity planning with supply chain and operations
• Own test engineering across multiple programs
• Build scalable test infra and documentation for future programs
• Contribute to DFT reviews, tapeout checklists, and test escape analysis
• Help mature internal test capabilities over time

Skills

5+ years semiconductor test

Hands-on DFT

ATPG/MBIST/JTAG

ATE test programs

external supplier collaboration

communication across time zones

Tools

Advantest

Teradyne

Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.

Efficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.

The right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers.

You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products.

What You Will Do

DFT Strategy and Pattern Development

• Partner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip program
• Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequences
• Develop and maintain STIL and PDL test program files for ATE execution
• Drive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partners
• Support setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initialization
• Understand and define power rail sequencing requirements for ATE execution to ensure safe device bringup

ATE Bringup and Test Program Development

• Develop and debug test programs on ATE platforms including Advantest and Teradyne systems
• Execute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams
• Characterize device behavior across voltage, temperature, and frequency corners
• Support load board bring-up and interface hardware validation
• Define and manage test flows including wafer probe, final test, and bin sort
• Understand test time optimization strategies such as pattern flow sequencing to minimize unnecessary power cycles

OSAT and Supplier Coordination

• Serve as the primary test engineering interface with OSAT partners and test houses
• Manage test program handoff to OSAT including documentation, qualification, and acceptance criteria
• Coordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF as required
• Track and analyze yield data from probe and final test, escalates anomalies, and drive corrective actions
• Support die traceability and OTP programming flows in production bin sort
• Coordinate with supply chain and operations on test capacity planning and lot scheduling
• Own test engineering across multiple active chip programs simultaneously
• Build scalable test infrastructure and documentation that carries forward to future programs
• Contribute to DFT reviews, tapeout checklists, and test escape analysis
• Help define and mature internal test engineering capabilities over time

What You Bring

Required

• 5+ years of semiconductor test engineering experience in a fabless or IDM environment
• Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scan
• Experience generating and validating STIL patterns and working with test pattern delivery packages
• ATE test program development experience on Advantest or Teradyne platforms
• Experience supporting wafer probe and final test at an OSAT or test house, including load board bringup
• Familiarity with power sequencing requirements and DFT entry flows for ATE test program development
• Ability to work directly with external design partners and OSAT suppliers to coordinate pattern delivery and test execution
• Strong written and verbal communication skills - this role requires ongoing collaboration with external partners across multiple time zones

Preferred

• Experience with embedded memory test including characterization and programming of non-volatile memory technologies
• Exposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocols
• Familiarity with DFT tools from major EDA vendors
• Experience at a fabless startup or small team where test engineering scope is broad
• Exposure to leading-edge process nodes at 28nm or below
• Experience with ATE yield analysis and test time optimization
• Scripting ability in Python or Perl for data analysis and test automation
• Experience generating VCD from RTL simulation and porting to STIL format

We offer a competitive salary for this role, generally ranging from $150,000 to $190,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility.